1. Field of the Invention
This invention relates to a power MOS FET having a decreased "on" resistance.
2. Description of the Prior Art
There has heretofore been proposed such a power MOS FET as shown in FIGS. 1A, 1B, for example, wherein an N.sup.+ type low-resistance drain region 8 and N.sup.- type high-resistance drain region (epitaxial layer) 7 are formed in a silicon wafer whose main face comprises the (100) face; and a P type well region 6 and an N.sup.+ type source region 5 are provided, in the named order and in the form of layers, on the epitaxial layer 7. In the layer regions 5, 6 and 7 is formed, by means of anisotropic etching of the (100) face, a V-shaped groove 10 which is oriented in the face (111). Furthermore, a vapor-deposited aluminum layer 1 is provided which is connected to the source region 5 through a silicon oxide layer 4, gate electrode layer 3, PSG layer 2 consisting of phosphor glass, and contact hole 9.
With the foregoing conventional construction, when a voltage is applied to a gate electrode G, a channel is formed, as indicated at 20, in the vicinity of that portion of the P type well region 6 which is in contact with the V-shaped groove 10, so that a drain current is permitted to flow from a drain electrode D toward a source electrode S.
However, the aforementioned conventional power MOS FET is disadvantageous in that the "on" resistance thereof is increased due to the fact that the current flowing through the drain regions 7 and 8 is caused to concentrate immediately below the V-shaped groove 10. To decrease the "on" resistance, it is required that the overall size of the element be increased.